A graphics systems typically utilizes a graphics pipeline that includes a raster operations (ROP) stage to perform raster operations on pixel data A ROP stage commonly performs several different operations on pixel data. These include performing Z depth test operations to determine visible pixels, discarding occluded pixels, and performing read/modify/write operations with a Z-buffer. A ROP may also perform frame buffer color blending operations such as combining colors, performing anti-aliasing operations, and read/modify/write operations with a color buffer.
A ROP stage performs a large number of memory accesses in order to perform raster operations on Z data and color data. The efficiency with which memory accesses can be performed is thus of concern in designing a graphics system.
There is increasing interest in the graphics industry in utilizing different rendering modes for specific applications. A rendering mode may, for example, have specified formats for Z data and color data. Certain game modes, for example, do not require certain types of data for rendering certain types of surfaces and/or require data of the same precision or type. Consequently, the number of bits required for Z data and color data may depend upon the rendering mode. However, in a graphics system supporting different rendering modes one or more of the rendering modes may not be efficient in regards to performing memory accesses.
Additionally, one or more of the rendering modes may not pack data efficiently. For example, U.S. patent Ser. No. 10/740,229, entitled “System and method for packing data in a tiled graphics memory,” commonly assigned to the assignee of the present invention, discloses an embodiment for packing 32 bits per pixel into different portions of a tile, where the 32 bits include 8 bits of stencil data and 24 bits of Z data per pixel. However, the tile format disclosed in U.S. patent Ser. No. 10/740,229 is inefficient in regards to packing efficiency when only 24 bit Z data is required, since only three-fourths of the storage capacity of the tile format is utilized (e.g., 24 bits/32 bits=¾). The contents of U.S. patent Ser. No. 10/740,229 is hereby incorporated by reference.
Therefore, in light of the above described problems the apparatus, system, and method of the present invention was developed.